It is well known that a four-layer sandwich of doped material NPNP, forms a silicon-controlled rectifier (SCR). Once an SCR is “fired” (switched to its ‘ON’ or conducting state), it continues to conduct until its gate signal is removed. In certain devices, an SCR can be unintentionally formed by the mere presence of interleaved N and P doped materials. The SCR is undesirable for certain applications, since inadvertent firing of an SCR will usually result in excessive current flow through the device. This excessive current flow can result in destructive failure of an integrated circuit with unintentionally formed SCRs.
Complementary-symmetry Metal-Oxide Semiconductor (CMOS) devices have parasitic SCR structures built in to the CMOS device. The inadvertent firing of a parasitic SCR in a CMOS device is termed latch-up. A CMOS designer therefore designs the CMOS device to avoid circuit latch-up, since a malfunction of the CMOS integrated circuit may occur caused by the firing of a parasitic PNPN structure inherent in the CMOS device. Latch-up, as used herein, means a state in which a low impedance path results from an overstress that triggers a parasitic SCR structure and that persists after removal or cessation of the trigger condition. Therefore, testing for latch-up during device testing is important to isolate devices with latch-up problems.